The present invention is directed, in general, to logical devices and, more specifically, to a clock signal selection system, a related method of generating a clock signal and a programmable clock manager including the system or the method.
Modern digital electronic computers include a number of cooperating sequential logic circuits that each perform several routine operations, and are each controlled by derivatives of a common clock signal. The clock signals should be synchronized at predetermined locations within the system to help optimize computer function. Although the individual clock signals may have a common source, they often do not arrive at their intended destinations in proper synchronism, for example due to variations in signal propagation delay for each destination. Thus, combining several complex sequential logic circuits within a system presents a challenge with respect to synchronizing the time frames between the respective circuits therein.
Because synchronous sequential logic circuits change states at the rising or falling edge of a synchronous clock signal, proper circuit operation often demands that any external input signals to the synchronous sequential logic circuit generate valid inputs that occur with the proper set up time and hold time requirements relative to the designated clock edge. However, in a system including sequential logic circuits having a master system clock that operates the several diverse system circuits, there is often a problem with skew (different amounts of delay in different portions of the device) between the system clock and the destination clock signals propagating through the various circuits.
As higher density programmable logic devices (PLDs) become available, on-chip clock distribution becomes more important to the integrity and performance of the designs implemented in these devices. Unfortunately, with the advent of high-density PLDs, such as a field programmable gate array (FPGA), difficulties in managing clock delay and clock skew associated with these devices has become substantial. Many existing solutions for these problems, such as hardwired clock trees, are less effective for the high density PLDs found in today""s programmable logic market. As integration levels of microelectronic circuits and system complexity continues to increase, the routing or distribution of a master system clock has become even more critical. This challenge is especially exacerbated in view of ever increasing clock rates in today""s powerful microprocessors.
A common solution to these problems is the incorporation of a programmable clock manager (PCM) into the PLDs themselves. A PCM may be used to adjust the clock frequency, the clock phase and the clock duty cycle for system clocks. Conventional PCMs may be found in either Phase-Locked-Loop (PLL) or Delay-Locked-Loop (DLL) architecture to assist in synchronizing clock signals in the PLD. Although DLL circuitry may be used to resolve some of the problems in today""s PLDs, employing a voltage controlled oscillator (VCO) to create a PLL architecture has continued to gain popularity among device designers, primarily due to its frequency synthesis capability.
A VCO generally adjusts the various signals, such that the edges of the internal clock signals are aligned with those of a master clock signal, even though the time frame of each signal is thereby shifted. The PLL architecture provides feedback that is used to nullify clock distribution delays within the circuit by comparing the phase of a master clock signal with that of a feedback signal. The difference between the two signals is used in a feedback control system to bring the first and second signals into a fixed phase relation. Logical elements such as an AND gate and divider logically combine the master clock signal with the feedback signal to provide a synchronization signal for the system. More specifically, the master clock signal is compared with the feedback signal and a reference (synchronization) signal is generated in response to the difference. Delay circuitry may be used to produce delays in the output clock signal based on a selected delay time, depending on the application of the output clock signal. Alternatively, delay compensation may be used to synchronize the master clock and feedback signals based on the reference signal. In this way, all circuits of the device receive synchronous clock signals and clock signal skew is reduced.
Although capable of performing such delay compensation, even the most advanced PCMs, whether employing PLL or DLL architecture, are unable to coordinate such delay compensation with other important functions such as frequency synthesis and duty cycle synthesis. Frequency synthesis involves altering the frequency of the output clock signal of the PCM with respect to the frequency of the master clock signal. Duty cycle synthesis involves selecting a duty cycle (e.g., the on/off time of a signal, independent of its frequency) of the output clock signal based on a desired application.
In conventional devices, multiple PCMs have been incorporated to perform all three functions within a system. Of course, with an increase in the number of PCMs employed in a programmable device comes a corresponding increase in the cost of manufacturing. These increased costs are inevitably passed down to the consumers. Alternatively, a combination of the PLL with DLL architectures have been attempted, but again resulting in increased manufacturing costs.
Accordingly, what is needed in the art is a PCM capable of performing frequency synthesis and duty cycle synthesis, as well as delay compensation, without suffering from the deficiencies found in the prior art.
To address the above-discussed deficiencies of the prior art, the present invention provides a selection system for use with a programmable clock manager (PCM) having an input signal. In one embodiment, the selection system includes a phase selector, having multiple taps, configured to generate multiple phase shifted signals from a reference signal corresponding to the input signal with a fixed phase shift therebetween. The phase selector is further configured to select at least two of the phase shifted signals. The selection system further includes a duty cycle synthesis circuit configured to generate a clock signal having a duty cycle as a function of a phase shift between the selected phase shifted signals.
In another aspect, the present invention provides a method of generating a clock signal. In this embodiment, the method includes developing multiple phase shifted signals, having a fixed phase shift therebetween, from a reference signal, selecting at least two of the phase shifted signals, and generating the clock signal having a duty cycle as a function of a phase shift between the selected phase shifted signals.
In yet another aspect, the present invention provides a PCM including a comparator circuit configured to determine whether a frequency and a phase of a feedback signal are substantially equal to a frequency and a phase of an input signal. In addition, the PCM includes a selection system having a phase selector, with multiple taps, configured to generate multiple phase shifted signals from a reference signal corresponding to the input signal with a fixed phase shift therebetween. The phase selector is further configured to select at least two of the phase shifted signals. The selection system also includes a duty cycle synthesis circuit configured to generate a clock signal having a duty cycle as a function of a phase shift between the selected phase shifted signals.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.